<p>Dear All
I plan to apply to MIT. I have written SOP that particularly answers the questions that are asked by the admission committee. I like all of you to cooment on my essay and suggest few improvements I can make.</p>
<p>Please explain why you are a good candidate for graduate school. You should describe why you wish to attend graduate school, what you would like to study, and any research experience you have. Describe one or more accomplishments you are particularly proud of that suggest that you will succeed in your chosen area of research.</p>
<p>Answer:
I aspire to take admission in PhD program offered by Department of Electrical Engineering and Computer Science (EECS) at MIT. I would like to work on low power designs and architectures. I have chosen this area for two reasons. First, Power Management has evolved as indicative of new trends in the microprocessor design. No wonder why Intel has found power management challenging while keeping pace with Moores law trajectory and IBMs 1bn dollar green Project addresses power issues. Secondly, there hangs by an event that seemed to pose a challenging but an interesting problem. My well-tested AT89C51 based data logger circuit rendered ineffective, once placed too close to my High temperature Laptop heat sink. The Microcontroller IC malfunctioned and showed uneven heat distribution along the surface. Why did Microprocessor emit so much heat? How did Microcontroller suffer from thermal runaway? Could we find a way to cool it down? While searching answers to these questions, I came across a paper that answered most of my questions. Not only did it provide me ample satisfaction but also motivated me to pursue my graduate studies at MIT.</p>
<p>It was a paper Reducing power density through activity migration by Seongmoo Heo, Kenneth Barr, and Krste Asanovi´c, appeared in (ISLPED), Seoul, Korea, August 2003. I was able to conclude from the paper that Silicon being poor conductor of heat was responsible for hot spots developing in microprocessor. Thermal runaway occurred due to the exponential dependency of leakage current on temperature demanded activity migration: the process wherein heat was spread by transporting computation load to a different location on the die. The paper helped me identify the exact area of my interest: The low power computer architecture.</p>
<p>My research objectives are based on finding low power techniques in dedicated architectures and microprocessors. Application specific architectures offer greater opportunities to minimize powerthe result I derived while working on parallel-pipelined FFT architecture. The initial intent to achieve parallelism yielded some astonishing results. The power hungry single Pipeline FIFO buffer when split up into parallel pipeline units reduced overall FIFO buffers data activity. I was able to prove mathematically that parallel-pipelined FIFO buffers tend to cut back on the probability of data transition on per cycle basis. The paper Superscalar and Power efficient architecture of FFT was presented in 8th Comsats Workshop on Research in Computing (CWRC), where it won the best paper award of the session and now it is approved for publication in IEEE IC-4: an achievement that I am particularly proud of.</p>
<p>As for high performance microprocessors, efficient power and thermal management are more critical as systems become smaller or more capable with every generation of Moores Law. I have observed that only specific portions of microarchitectural units that make hot regions for a given block of the program. This is in accordance with the intensive research that shows similar results. These studies, however, undermine statistical analysis of application programs when it comes to optimize power consumption for the specific microarchitectural unit: register file, in particular. I believe we can skimp on significant amount of power by logically isolating hot regions from within the parent unit for each segment of the program based upon the type of reference made. For instance, the statistics of different benchmarks show that most register file references are reads and only few registers are allocated for this purpose. They can be accommodated into logically isolated read dominant (LIRD) register file specialized to entertain reads. The isolated and distributed nature of microarchitectural units can also facilitate activity migration that prevents the formation of hot spots inside CPU. I would like to work intensively to experiment this logical splitting in my graduate thesis work.</p>
<p>I wish to attend the graduate school since it marks new research landscapes. A graduate school program envisions new trends in industry and provides ground floor of innovation. I have specifically chosen MIT not just for the reason that MIT provides research domains that match my interest and I seek fulfillment of my career goals; but also for the opportunities of industrial research and collaboration. For instance, Researchers at MIT and Texas Instruments had recently unveiled a new chip design for portable electronics that can be up to ten times more energy-efficient than present technology. The project also involved two EECS students. I am particularly interested in, the SCALE sub-group Low Power which attempts to remodel individual components of CPU to minimize overall power. Load sensitive flip-flops, Low power 32-bit Datapath designs and Low power single precision IEEE FPUs represent such examples. Similarly, the Energy Exposed Instruction Set group is discovering state-of-the art techniques of exposing microarchitecture to the software. Dr. Krste Asanovic and his team, propose that if we expose energy consumption to software we can skimp on run time energy by making certain compile time decisions. This can be achieved through program restart markers and tag unchecked load-stores as he mentions in one of his paper. It took me some time to get to the basics of his work but it will be great honor if I get an opportunity to work under his supervision at CSAIL.</p>
<p>I took my undergraduate courses as preparation for prospective graduate studies, which require problem oriented rigorous learning. I was able to emulate this methodology, even in my BSc where I would try to find solution to most problems with simulations and experimentation. It helped me gain some insight of the fundamentals of research. It was only through self-motivation, that I was able to publish my first ever paper on new efficient sorting algorithm in Intel Sponsored 2nd IEE APEC 2005. Participating in such competitive event was indeed a priceless experience and significant achievement for an undergrad. I also learned to make teaching and research grow together when started my professional career as Lecturer. Since graduate programs entail more effort on the part of student than the magnitude of supervision available, I established loosely supervised learning paradigm where I first identified area of interest of my own after having analyzed the problem and then began referring to books and papers. I also selected few good students to work with me. I love to share my findings with the students. IET Student Chapter University of Engineering and Technology Lahore invited me to deliver talk on Low power Computer Architecture. My personal website [Welcome</a> to Ahsan’s page](<a href=“Yahoo | Mail, Weather, Search, Politics, News, Finance, Sports & Videos”>Yahoo | Mail, Weather, Search, Politics, News, Finance, Sports & Videos) highlights my academic activities. My career as an academic professional finds me in a good place to be a successful graduate student leading to an independent academic researcher.</p>
<p>Driven by deep interest in computing and microprocessors, the prevalent theme of computer architecture runs through both my academic and professional career, based on my deep interest, aptitude and past research experience; I believe I can prosper in my chosen area of research.</p>